1. Field of the Invention
The present invention relates to an optical receiver device for receiving optical signals modulated using Differential Quadrature Phase Shift Keying (DQPSK) in an optical transmission system.
2. Description of the Related Art
In recent years, an optical transmission system which employs the DQPSK modulation is proposed as one of solutions for expanding bandwidth in an optical communication network (for example, see Patent Document 1 below). In this modulation method, two bits of information are transmitted in one symbol, thereby, a bit rate of 40 Gb/s at a modulation rate of 20 Gbaud/s is realized. In this optical transmission system, an optical. transmitter device modulates optical carrier waves using the DQPSK and transmits them as the optical signals, and an optical receiver device demodulates the received optical signals and extracts the data.
Patent Document 1
Publication in Japan of translation of PCT International Patent Application: No. 2004-516743
FIG. 1A shows a configuration of a DQPSK receiver used in a conventional optical receiver device. This DQPSK receiver comprises an optical splitter 11, delay interferometers 12-1 and 12-2, photodiodes 13-1, 13-2, 13-3 and 13-4, transimpedance amplifiers (TIA) 14-1 and 14-2, limiting amplifiers (LIA) 15-1 and 15-2, a clock recovery circuit (CR) 16, decision circuits (DEC) 17-1 and 17-2 and a 2-to-1 multiplexer (MUX) 18.
Two optical signals split by the optical splitter 11 are respectively input into the delay interferometers 12-1 and 12-2. In these optical signals, as relative phase values with respect to the previous signal by one symbol, four phases of π/4, 3π/4, −π/4 and −3π/4 are used.
The delay interferometer 12-1 splits the input optical signal into two signals, delays one optical signal by one symbol using a delay generator 21-1, gives a phase shift of π/4 to the other optical signal using a phase shifter 22. Then, the delay interferometer 12-1 extracts phase modulation components by causing the two optical signals from the delay generator 21-1 and the phase shifter 22 to interfere with each other, and outputs the extracted phase modulation components to the photodiodes 13-1 and 13-2.
The delay interferometer 12-2 splits the input optical signal into two signals, delays one optical signal by one symbol using a delay generator 21-2, gives a phase shift of −π/4 to the other optical signal using a phase shifter 23. Then, the delay interferometer 12-2 extracts phase modulation components by causing the two optical signals from the delay generator 21-2 and the phase shifter 23 to interfere with each other, and outputs the extracted phase modulation components to the photodiodes 13-3 and 13-4.
In the above manner, the two phase modulation components which are orthogonal to each other are extracted from the received optical signal by the delay interferometers 12-1 and 12-2, and the extracted phase modulation components are converted into variation of light intensity to be output.
The photodiodes 13-1 and 13-2 forms balanced photodiodes to convert the optical signals output from the delay interferometer 12-1 into an electric current by the photoelectric conversion and to output the electric current. The transimpedance amplifier 14-1 conducts a current-voltage conversion. The amplifier 15-1 amplifies the converted electric signal and outputs the amplified signal to the decision circuit 17-1 as the first data signal.
Similarly, the photodiodes 13-3 and 13-4 convert the optical signals output from the delay interferometer 12-2 into an electric current. The transimpedance amplifier 14-2 conducts a current-voltage conversion. The amplifier 15-2 amplifies the electric signal and outputs the amplified signal to the decision circuit 17-2 as the second data signal. In this manner, the received optical signal is detected and the data is extracted from the input signal.
The clock recovery circuit 16 extracts a clock signal from the first data signal input to the decision circuit 17-1, and distributes the signal to the decision circuits 17-1 and 17-2. The decision circuits 17-1 and 17-2 are configured by using for example D flip-flop circuits, respectively latches the first data signal and the second data signal in accordance with the extracted clock signals, and outputs the signals to the multiplexer 18. The multiplexer 18 multiplexes the two data signals from the decision circuits 17-1 and 17-2, and transfers the multiplexed signal to a deserializer (not shown) at a later stage.
For example, when quadrature signal Q and in-phase signal I as shown in FIG. 1B are respectively obtained as the first data signal and the second data signal, the multiplexer 18 multiplexes these signals in order to produce the original data string “ABCDEF . . . ”.
When the in-phase signal I and the quadrature signal Q as shown in FIG. 1C are respectively obtained as the first data signal and the second data signal, the multiplexer 18 multiplexes these signals and produces a data string “BADCFE . . . ”. However, the produced data string is different from the original data string “ABCDEF . . . ”, accordingly, a bit swap function have to be provided in the multiplexer 18 or in a circuit (framer or the like) at a later stage for swapping adjacent data. In this case, the invention described in Japan Patent Application No. 2005-206467 can be utilized, which is a prior application.
FIG. 1D is a timing chart showing an example of input and output signals of the decision circuits 17-1 and 17-2. In this example, the signals input to the decision circuits 17-1 and 17-2 are latched by the rising edges of the clock signal and the output data signals are produced.
However, the above described conventional DQPSK receiver has problems as below.
As shown in FIG. 1A, the conventional DQPSK receiver employs a configuration in which two decision circuits 17-1 and 17-2 operates in accordance with the clock signal extracted by the single clock recovery circuit 16. The timing chart shown in FIG. 1D shows no differential delay between the data signals input to the decision circuits 17-1 and 17-2, however, a differential delay of ΔT actually occurs between the two input data signals as shown in FIG. 1E.
As shown in FIG. 1F, this differential delay of ΔT is equivalent to a difference of |Ta−Tb| between the delay time Ta from the input terminal of the optical splitter 11 to the input terminal of the decision circuit 17-1 and the delay time Tb from the input terminal of the optical splitter 11 to the input terminal of the decision circuit 17-2. In the DQPSK receiver, the differential delay of ΔT is required to be sufficiently smaller than the input phase margin of the multiplexer 18.
The electric circuit and the delay interferometers 12-1 and 12-2 made of PLCs (Planar Lightwave Circuits) in the DQPSK receiver can be manufactured such that a physical length difference is equal to or smaller than 1 mm to 2 mm (about 10 ps). Accordingly, the differential delay there is equal to or smaller than the input phase margin (25 ps to 35 ps) of the multiplexer 18 in the case of employing the time slot of 20 Gb/s (50 ps).
However, in the case where there is a fiber interface between the optical splitter 11 and the delay interferometers 12-1/12-2 such as the case where the optical splitter 11 is provided as an external device, it is difficult to fabricate fibers exactly in the equal length if fusion splice is taken into consideration, which results in the difference of about 1 cm. The difference of 1 cm is equivalent to the differential delay of about 50 ps, and to the shift by one bit at the transmission rate of 20 Gb/s, which results in a serious problem and requires an initial adjustment.
In this case, almost the entirety of the differential delay ΔT consists of the difference between the delay time Ta1 from the input terminal of the optical splitter 11 to the input terminal of the delay interferometer 12-1 and the delay time Tb1 from the input terminal of the optical splitter 11 to the input terminal of the delay interferometer 12-2, i.e., |Ta1−Tb1|.
Further, the differential delay between the data signals output from the decision circuits 17-1 and 17-2 which are to be input to the multiplexer 18 has to be suppressed to a sufficiently small value such as about 10 ps to 15 ps compared to the phase margin.
In the invention described in Japan Patent Application No. 2005-245071 employs the configuration in which a delay amount of the data signals is adjusted using a variable delay circuit. However, manufacture of the conventional variable delay circuit which is commonly used supposes the use of CMOS (Complementary Metal Oxide Semiconductor), and the operation at 20 Gb/s cannot be realized by the current circuit technology. It is also thought that manufacture of the circuit having the same function with Silicon-Germanium is not practical in view of scale of the circuit and the electric power consumption.